基于高层次融合的卷积神经网络FPGA硬件加速

魏楚亮; 陈儒林; 高谦; 孙正隆

doi:10.3788/OPE.20202805.1212

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基于高层次融合的卷积神经网络FPGA硬件加速

信息科学 | 更新时间：2020-07-09

- 基于高层次融合的卷积神经网络FPGA硬件加速
- FPGA-based hardware acceleration for CNNs developed using high-Level synthesis
- 光学精密工程 2020年28卷第5期页码：1212-1219
- 作者机构：
  
  1.汕头大学电子工程系, 广东汕头 515063
  2.深圳市人工智能与机器人研究院, 广东深圳 518054
  3.香港中文大学(深圳) 理工学院, 广东深圳 518172
- 作者简介：
  
  [ "魏楚亮(1979-)，男，广东揭阳人，博士，副教授，2006年于英国利物浦大学获得博士学位，主要从事人工智能、机器人、传感技术、智能工业控制、交通运输安全检测、FPGA设计等的研究。E-mail: clwei@stu.edu.cn" ]
  陈儒林(1998-)，男，广东茂名人，主要从事机器学习、FPGA设计等的研究。E-mail: 16rlchen@stu.edu.cn CHEN Ru-lin, E-mail: 16rlchen@stu.edu.cn
- 基金信息：
  
  广东省普通高校特色创新项目(2018KTSCX061);揭阳市科技计划项目(2019007 & 2019065);广东省重大科技专项(2015B020233018);深圳市人工智能与机器人研究院项目(2019-INT010)
- DOI：10.3788/OPE.20202805.1212
  中图分类号： TP18;TP391.4
- 收稿日期：2019-12-10，
  
  修回日期：2020-02-03，
  
  录用日期：2020-2-3，
  
  纸质出版日期：2020-05-25
- 稿件说明：
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魏楚亮, 陈儒林, 高谦, 等. 基于高层次融合的卷积神经网络FPGA硬件加速[J]. 光学精密工程, 2020,28(5):1212-1219.

Chu-liang WEI, Ru-lin CHEN, Qian GAO, et al. FPGA-based hardware acceleration for CNNs developed using high-Level synthesis[J]. Optics and precision engineering, 2020, 28(5): 1212-1219.
魏楚亮, 陈儒林, 高谦, 等. 基于高层次融合的卷积神经网络FPGA硬件加速[J]. 光学精密工程, 2020,28(5):1212-1219. DOI： 10.3788/OPE.20202805.1212.

Chu-liang WEI, Ru-lin CHEN, Qian GAO, et al. FPGA-based hardware acceleration for CNNs developed using high-Level synthesis[J]. Optics and precision engineering, 2020, 28(5): 1212-1219. DOI： 10.3788/OPE.20202805.1212.

摘要

为了解决神经网络前向传播过程中的硬件加速问题，设计了一套基于FPGA编程工具Vivado HLS开发的AlexNet神经网络前向传播硬件加速系统。该系统能够确保在达到相关应用要求的基础上，有效地节省开发时间并降低开发成本。系统基于高级计算机语言C++进行FPGA电路的仿真与开发，同时，灵活运用具有很高便捷性及可靠性的Vivado HLS中的PIPELINE和ARRAY_PARTITION指令进行系统优化。实验结果表明，AlexNet神经网络在本文所构建的FPGA加速系统上的运行时间为21.95 ms，比在传统GPU平台上的运行时70 ms少，运行速度要3倍以上。此外，每一层的网络都实现了分开封装操作，使系统可便捷地移植到其它成熟的卷积神经网络上，加速了深度学习在各类人工智能系统上的应用，在智能产业具有广泛的应用价值。

Abstract

To accelerate the forward-propagation process of deep-learning networks

a field-programmable gate array (FPGA) hardware-acceleration system for AlexNet was developed using Vivado High-Level Synthesis (HLS)

which can greatly reduce the FPGA development cost. Using Vivado HLS

developers can design hardware architectures on an FPGA platform using C/C++ code instead of a hardware-description language. We implemented AlexNet on an FPGA platform using the HLS tool

and then used the PIPELINE and ARRAY_PARTITION directives to optimize the proposed system. An evaluation of the proposed system shows that its performance is three times better than a traditional computing-platform graphics processing unit (GPU). In the future

owing to the high-level encapsulation

the developed system can be easily transformed into other convolutional neural networks for practical operation

which shows its great portability and practical application value.

关键词

Keywords

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